S. Ramesh
S. Ramesh
S. Ramesh is a Technical Fellow at the General Motors India Science Laboratory in Bangalore, India. As a technical fellow, he plays a key role in setting up a Centre of Excellence in rigorous control software engineering for automotive embedded systems. As part of this Centre, he is involved in directing a group of young researchers in devising and developing rigorous methods and tools for model-based development and verification of distributed embedded software.
S. Ramesh has more than 20 years of research experience in the areas of high level language design, validation and verification of distributed systems, embedded software and hardware designs. Earlier, he was a Professor in the Dept of Computer Science and Engineering, Indian Institute of Technology, Bombay. At IIT Bombay, he was also the head of the Centre for Formal Design and Verification of Software which he co-founded. As part of the Center activities, he carried out many industry-sponsored projects on verification of hardware and embedded software.
S. Ramesh has been actively involved in many national and international collaborative research projects. He has published more than sixty papers in international conferences and journals, co-edited a few conference and workshop proceedings, special issues in international journals, been panelists and on the program committee for many International conferences, and refereed several papers for many international journals and conferences
Selected Publications
(see http://www.informatik.uni-trier.de/~ley/db/indices/a-tree/r/Ramesh:S=.html for more details)
| [1] | Interprocedural Slicing of Multithreaded Programs with Applications to Java, Vol. 28 (6), ACM TOPLAS 2006 (with M. Gowri). | |
| [2] | Test Case Generation from Formal Models through Abstraction Refinement and Model Checking, Proc. of AMOST 2007. (with M. Satpathy) | |
| [3] | A Formal Framework for the Correct-by-Construction and Verification of Distributed Time Triggered Systems, Proc. of SIES, IEEE Press, July 2007. (with Prasanna Vignesh and Gurulingesh Raravi) | |
| [4] | Testing Model Processing Tools for Embedded Systems, Proc. of RTAS07, IEEE Press, March 2007. (with P. Sampath, K. C. Sashidhar and Rajeev A.C.) | |
| [5] | Synthesis of Synchronous Interfaces, Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), IEEE CS Press, 2006 (with Purandar Bhaduri) | |
| [6] | Automated Synthesis of Assertion Monitors Using Visual Specification, Proc. of IEEE/ACM International Conference on Design Automation and Test Europe, DATE 2005, Munich, February 2005 (with A. Gadkari). | |
| [7] | Synchronous Protocol Automata for Modelling and Verification of SoC Communication Architectures, IEE Proc. Computers \& Digital Techniques, 2004 (with V.J. D'Silva and A. Sowmya) | |
| [8] | Synchronous Protocol Automata for Modelling and Verification of System-on-Chip Bus Architectures, Proc. of IEEE/ACM International Conference on DATE, IEEE Press, February 2004. (with V.J. D'Silva and A. Sowmya). | |
| [9] | Forced Simulation: A Technique for Automating Component Reuse in Embedded Systems, ACM Trans. On Design Automation of Electronic Systems, Vol.6 No. 4, October 2001. (with Partha S. Roop and A. Sowmya) | |
| [10] | Apportioning: A Technique for Efficient Reachability Analysis of Concurrent Object Oriented Programs, IEEE Trans. on Software Engineering, Vol. 27, No. 11, 2001. (with Sridhar Iyer) | |
| [11] | Slicing Concurrent Programs, Proc. ACM SIGSOFT International Conference on Software Testing and Analysis (ISSTA 2000), ACM Press, August 2000 (with M. Gowri Nanda) | |
| [12] | Languages for Asynchronoy and Synchrony, Int. Journal of Foundations of Computer Science, June 2000 (with R.K. Shyamasundar) | |
| [13] | Extending Statecharts with Temporal Logic, IEEE Transaction on Software Engineering, Vol. 24, No. 3, March 1998. (with A. Sowmya) | |
| [14] | Validation of Pipelined Processor Designs using Esterel Tools: A Case Study, Proc. of CAV '99, LNCS Vol. 1633, 1999. (with P. Bhaduri) | |
| [15] | A direct Characterization of Completion, Journal of Theoretical Computer Scince A, Vol. 154, February 1996. (with Srinivas B.N.) | |
| [16] | Communicating Reactive Processes, Proc. of 20th Annual ACM SIGPLAN-SIGACT Symposium on POPL, January, 1993 (with Berry,G., and Shyamasundar, R.K.) |
